Phase indication apparatus

ABSTRACT

A variety of embodiments may include a voltage controlled oscillator to generate a differential signal on two nodes; and phase detector to compare a phase of the differential signal and a phase of a received signal, the phase detector including a sampling circuit to periodically sample voltage values on the two nodes, and a linear voltage-to-current converter responsive to the voltage values to create a control voltage for the voltage controlled oscillator.

[0001] This application is a divisional of U.S. patent application Ser.No. 10/146,689, filed on May 14, 2002, which is a divisional of U.S.patent application Ser. No. 09/735,858, filed on Dec. 13, 2000, nowissued as U.S. Pat. No. 6,420,912, which are both incorporated herein byreference.

FIELD

[0002] Various embodiments may relate generally to voltage-to-currentconverters, including linear voltage-to-current converters, and phaseindication apparatus, such as phase lock loop circuitry.

BACKGROUND

[0003] Phase lock loop (PLL) circuits and delay lock loop (DLL) circuitsare commonly used in integrated circuits today. Example uses for thesecircuits include clock recovery in communications systems and clocksignal alignment in digital systems.

[0004] PLLs and DLLs often incorporate a phase detector and a voltagecontrolled oscillator (VCO). The VCO generates an output signal with aphase and frequency that is a function of a control voltage. The phasedetector measures the phase difference between an input signal and theoutput signal, and adjusts the control voltage of the VCO. The controlvoltage to the VCO represents a phase difference, or “phase error”between the input signal and the output signal. When the phase error islarge enough, the VCO changes the phase or frequency of the outputsignal to more closely match that of the input signal.

[0005] Examples of PLLs, DLLs, VCOs, and phase detectors are describedin: Ian A. Young, Jeffrey K. Greason, and Keng L. Wong, “A PLL ClockGenerator with 5 to 110 MHz of Lock Range for Microprocessors,” IEEEJournal of Solid-State Circuits, pp. 1599-1607, Vol. 27, No. 11,November 1992; and Henrik O. Johansson, “A Simple Precharged CMOS PhaseFrequency Detector,” IEEE Journal of Solid-State Circuits, pp. 295-299,Vol. 33, No. 2, February 1998.

[0006] The phase detectors described in the above references exhibit a“dead zone” in the phase characteristic at the equilibrium point undercertain conditions. The dead zone generates phase jitter in part becausethe VCO does not change the phase of the output signal when the phaseerror is within the dead zone. As the operating frequency of integratedcircuits increases, PLLs, DLLs, and their associated VCOs and phasedetectors are also operating faster, and the size of the dead zonebecomes an important factor in the design of circuits.

[0007] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternate phase detectors and circuits that incorporate phase detectors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 shows a phase lock loop;

[0009]FIG. 2 shows a phase detector;

[0010]FIG. 3 shows sampling circuit waveforms;

[0011]FIG. 4 shows a block diagram of a voltage-to-current circuit;

[0012]FIG. 5 shows a circuit diagram of a voltage-to-current circuit;

[0013]FIGS. 6A-6C show graphical results of a simulation of the circuitof FIG. 5; and

[0014]FIG. 7 shows an integrated circuit having a phase lock loop.

DETAILED DESCRIPTION

[0015] The method and apparatus of the various embodiments of theinvention may provide a mechanism to convert a voltage to a current.Some embodiments may combine the voltage-to-current circuit with asampling circuit to implement a phase detector circuit. Two polaritiesof a differential signal can be sampled, and the voltage differencebetween the two polarities of the differential signal may be providd asan input to the voltage-to-current circuit. The voltage-to-currentcircuit may be a linear circuit that combines two complementaryvoltage-to-current circuits with a common gate output stage.

[0016]FIG. 1 shows a phase lock loop (PLL). PLL 100 may include a phasedetector 106, voltage controlled oscillator (VCO) 110, and frequencydivider 114. Phase detector 106 may receive an input clock signal onnode 102, and a clock signal on node 104. Phase detector 106 may measurea phase difference between signals on nodes 102 and 104, and generate avoltage on node 108 that is a function of the phase difference. VCO 110may receive the voltage on node 108, and produce an output clock signalon node 112.

[0017] Signals on nodes 102 and 104 can be single-ended or differentialsignals. For example, the input clock signal on node 102 can include asingle signal, or two signals that are complements of each other.Likewise, the signal on node 104 can include a single signal, or twosignals that are complements of each other. When a node carries adifferential signal, that node may includes multiple physical signaltraces. For example, in embodiments where the input clock signal is adifferential signal, node 102 includes two physical signal traces tocarry the differential signals. In some embodiments, VCO 110 produces adifferential clock signal on node 112, and frequency divider 114produces a differential signal on node 104.

[0018] In some embodiments, VCO 110 produces an output clock signal onnode 112 that has a frequency other than the frequency of the inputclock signal on node 102. For example, in some embodiments, PLL 100 isincluded in a microprocessor having an internal operating frequencyhigher than an external clock frequency. In these embodiments, PLL 100can generate an output clock signal at a greater frequency than an inputclock signal, but with matching phase.

[0019] In the embodiment shown in FIG. 1, VCO 110 may produce an outputclock signal having a frequency higher than the input clock frequency,and frequency divider 114 divides the output clock signal on node 112 toproduce a frequency divided signal on node 104. In some embodiments, VCO110 may produce an output clock signal at the same frequency as theinput clock signal, and frequency divider 114 is not included in PLL100. For ease of explanation, the remainder of this descriptiondescribes PLLs, phase detectors, and other circuits operating withsignals of the same frequency.

[0020]FIG. 2 shows a phase detector. Phase detector 200 may includesampling circuit 210, voltage-to-current circuit 230, and capacitor 250.Sampling circuit 210 may include switches 212 and 214 controlled by asignal on node 202. In the embodiment of FIG. 2, the signal on node 202is labeled “CLOCK1.”CLOCK1 is one of two signals input to samplingcircuit 210. The other signal input to sampling circuit 210 may be adifferential signal consisting of two physical signals received on nodes204 and 206 that are labeled “CLOCK2+” and CLOCK2−,” respectively. Takentogether, CLOCK2+ and CLOCK2− represent a single signal represented bythe label “CLOCK2.”

[0021] CLOCK1 and CLOCK2 correspond to signals on nodes 102 and 104 inFIG. 1. For example, in some embodiments, CLOCK1 corresponds to theinput clock signal on node 102 (FIG. 1), and CLOCK2 corresponds to theclock signal on node 104 (FIG. 1). In these embodiments, frequencydivider 114 (FIG. 1) produces a differential signal on node 104. Inother embodiments, CLOCK2 corresponds to the input clock signal on node102, and CLOCK1 corresponds to the clock signal on node 104. In theseembodiments, the input clock signal received on node 102 is adifferential signal.

[0022] Sampling circuit 210 may sample voltage values of differentialsignal CLOCK2 at transition points of CLOCK1, and produce a voltagedifferential (V_(dif)) between nodes 220 and 222. V_(dif) may representa phase error between CLOCK1 and CLOCK2. Sampling circuit 210 can beimplemented using known techniques for sampling signals.

[0023] Voltage-to-current circuit 230 may receive V_(dif) on nodes 220and 222 and produces a current on node 240. The current on node 240 maycharge and discharge capacitor 250 to produce a voltage for controllinga VCO, such as VCO 110 (FIG. 1). Voltage-to-current circuit 230 may be alinear circuit that produces a current on node 240 without a dead zone,or with a very small dead zone. When V_(dif) is positive,voltage-to-current circuit 230 may source an output current to chargecapacitor 250 to a higher voltage. In contrast, when V_(dif) isnegative, voltage-to-current circuit 230 may sink an output current todischarge capacitor 250 to a lower voltage.

[0024]FIG. 3 shows sampling circuit waveforms for signals CLOCK1 andCLOCK2 of FIG. 2. CLOCK1 is represented by waveform 306, CLOCK2+ isrepresented by waveform 304, and CLOCK2− is represented by waveform 302.CLOCK2+ and CLOCK2− are sampled at transition points of CLOCK1. This isshown at times 310 and 320 in FIG. 3. In the embodiment of FIG. 3, thetransition point is the rising edge of CLOCK1. In other embodiments, thetransition is the falling edge of CLOCK1.

[0025] At time 310, CLOCK2 is sampled and V_(dif) exists between points312 and 314. At time 320, CLOCK2 is again sampled and V_(dif) existsbetween points 322 and 324. As a result of V_(dif), voltage-to-currentcircuit 230 (FIG. 2) may change a control voltage for a VCO, which inturn may modify the phase of either CLOCK1 or CLOCK2 to reduce the phaseerror.

[0026]FIG. 4 shows a block diagram of a voltage-to-current circuit.Voltage-to-current circuit 230 may include NMOS-input voltage-to-current(V-I) converter 402, PMOS-input V-I converter 404, and output stage 406.Both NMOS-input V-I converter 402 and PMOS-input V-I converter 404 mayreceive V_(dif) on nodes 220 and 222. When V_(dif) is positive,NMOS-input V-I converter 402 may source current 420 on node 408, andPMOS-input V-I converter 404 may not contribute to the output current.Current 420 is labeled I_(ON) in FIG. 4. When V_(dif) is negative,NMOS-input V-I converter 402 may not contribute to the output current,and PMOS-input V-I converter 404 may sink current 422 on node 410.Current 422 is labeled I_(OP) in FIG. 4.

[0027] Output stage 406 can combine currents 420 and 422 to produceoutput current 424, labeled I_(O) in FIG. 4. Output stage 406 may reducethe sensitivity of the output current for different output voltages.

[0028]FIG. 5 shows a circuit diagram of a voltage-to-current (V-I)circuit. V-I circuit 500 may include transconductance amplifiers 520 and540, current mirrors 510 and 530, and output stage 406. Transconductanceamplifier 520 and current mirror 510, taken together, may represent oneembodiment of NMOS-input V-I converter 402 (FIG. 4). Likewise,transconductance amplifier 540 and current mirror 530, taken together,may represent one embodiment of PMOS-input V-I converter 404 (FIG. 4).Each of these circuits may be coupled between upper power supply node502 and lower power supply node 504.

[0029] Transconductance amplifier 520 may include n-channel inputtransistors 522 and 524. N-channel input transistors 522 and 524 areshown as n-channel metal oxide semiconductor field effect transistors(MOSFETs), and represent any type of transistor having an n-typechannel. The terms “NMOS” and “n-channel” are used herein to describesuch a transistor. Likewise, the terms “PMOS” and “p-channel” are usedherein to describe transistors having p-type channels. Transconductanceamplifiers of the type shown as transconductance amplifier 520 in FIG. 5are described in: S. C. Huang and M. Ismail, “Linear Tunable COMFETTransconductor,” Electronics Letters, pp. 459-461, Vol. 29, No. 5, March1993. Transconductance amplifiers 520 and 540 may include bias nodes toreceive bias voltages VB1 and VB2, respectively. In some embodiments,VB1 and VB2 are adjustable control voltages of the V-I converters toreduce process, temperature, and power supply variations.

[0030] Current mirror 510 may include p-channel transistors 512 and 514.P-channel transistor 512 may be diode connected, and have a gate coupledto the gate of p-channel transistor 514. The source-to-drain current intransistors 512 and 514 may be, therefore, substantially equal. AsV_(dif) changes, the gate voltage on n-channel transistors 522 and 524may also change. As the gate voltage changes, the drain-to-sourcecurrent in transistors 522 and 524 may change. The constant current incurrent mirror 510, and the varying currents in the n-channel inputtransistors of transconductance amplifier 520 may result in a varyingcurrent 420. When V_(dif) is positive, current 420 may flow in thedirection of the arrow shown in FIG. 5. When V_(dif) is negative,current 420 may not flow. This is due in part to the operation of outputstage 406, discussed in more detail below.

[0031] Transconductance amplifier 540 may be a complementary version oftransconductance amplifier 520. Transconductance amplifier 540 mayinclude p-channel input transistors 542 and 544. Current mirror 530 mayinclude n-channel transistors 532 and 534. N-channel transistor 532 maybe a diode connected transistor having a gate coupled in common with agate of n-channel transistor 534. As a result, drain-to-source currentsin transistors 532 and 534 may be substantially equal. As V_(dif) onnodes 220 and 222 varies, so may the source-to-drain current inp-channel input transistors 542 and 544. As a result, current 422 may beproduced. When V_(dif) is negative, current 422 may flow in thedirection shown by the arrow in FIG. 5. When V_(dif) is positive,current 422 may not flow, in part because of the operation of outputstage 406.

[0032] Output stage 406 may be a common gate output stage having twopairs of complementary transistors with gates coupled in common. Forexample, p-channel transistor 556 and n-channel transistor 558 may forma series connected complementary pair coupled between the output node ofthe NMOS-input V-I converter and the output node of the PMOS-input V-Iconverter. A junction between transistors 556 and 558 may form outputnode 240 of V-I converter 500. P-channel transistor 550 and n-channeltransistor 552 may form a series connected complementary pair oftransistor coupled between the upper power supply node and the lowerpower supply node. Gates of transistors within output stage 406 may allbe coupled in common with node 554 formed at the junction betweenp-channel transistor 550 and n-channel transistor 552. In this manner,transistors 550 and 552 may form a bias circuit to provide a gate biasfor transistors 556 and 558. In other embodiments, different biascircuits are used to bias transistors 556 and 558.

[0033] In operation, when V_(dif) is positive, p-channel transistor 556may be on and n-channel transistor 558 may be off. This allows current420 to flow as current 424 on output node 240. When V_(dif) is negative,n-channel transistor 558 may be on and p-channel transistor 556 may beoff, allowing current 424 to flow in the direction opposite the arrowshown in FIG. 5 to discharge capacitance on output node 240. Theoperation of the V-I converter 500 has been simulated in a 0.16 microncomplementary metal-oxide semiconductor (CMOS) process. Graphicalresults from the simulation are shown and described with reference toFIGS. 6A-6C.

[0034]FIGS. 6A-6C show graphical results of a simulation of the circuitof FIG. 5. FIG. 6A shows output current 424 (FIG. 5) as a function ofinput differential voltage V_(dif). Graph 600 shows the differentialmode gain at curve 610. Curve 610 represents the differential mode gainof V-I converter 500, as well as the individual differential mode gainsof the NMOS-input and PMOS-input converters without output stage 406.The output current various substantially monotonically from −0.44 to0.44 mA as the input differential voltage increases from −1.5 volts to1.5 volts. The output current of V-I converter 500 (FIG. 5) utilizes theNMOS-input V-I converter while the input differential voltage ispositive, and utilizes the PMOS-input V-I converter while the inputdifferential voltage is negative. This complementary operation exhibitsa large input differential voltage range, which may be applied tocircuits that can benefit from a linear V-I relationship.

[0035]FIG. 6B shows output current 424 (FIG. 5) as a function of inputcommon mode voltage. Graph 620 shows curves 622, 624, and 626. Curve 622represents output current 424 of V-I converter 500. Curves 624 and 626represent the output currents of the NMOS-input and PMOS-input V-Iconverters, respectively, when operating without each other and withoutoutput stage 406. Output current 424 varies within −6 uA to 4 uA as thetwo input signals increase from 0 volts to 1.5 volts, as shown by curve622. This common mode variation is generally smaller than variations ofthe individual NMOS-input and PMOS-input V-I converters. This is shownby the contrast between curves 622 and 624, and also by the contrastbetween curves 622 and 626.

[0036]FIG. 6C shows the effect of the output voltage on the outputcurrent. Graph 630 shows curves 632, 634, and 636. Curve 632 representsoutput current 424 (FIG. 5) of V-I converter 500. Curves 634 and 636represent the output currents of the NMOS-input and PMOS-input V-Iconverters, respectively, when operating without each other and withoutoutput stage 406. The data for curve 632 was generated with V_(dif) setto zero, and each of input nodes 220 and 222 biased at 0.75 volts.Output current 424 is close to zero when the output voltage is in therange of 0.5 volts to 1.0 volts. This is in contrast to the behavior ofthe NMOS-input and PMOS-input V-I converters operating without outputstage 406. This is shown by the contrast between curves 632 and 634, andalso by the contrast between curves 632 and 636.

[0037]FIG. 7 shows an integrated circuit having a phase lock loop.Integrated circuit 700 may include PLL 702 and sequential elements 706,708, and 710. PLL 702 may receive an external clock on node 722 andproduce an internal clock on node 704. PLL 702 can be any PLL embodimentdisclosed herein. For example, PLL 702 can incorporate phase detector200 (FIG. 2), and V-I circuit 500 (FIG. 5). Sequential elements 706,708, and 710 are shown as D-type flip-flops clocked by the internalclock on node 704, but this is not a limitation on embodiments of thepresent invention. For example, PLL 702 can create a clock signal thatdrives latches, flip-flops other than D-type flip-flops, or any othertype of sequential element.

[0038] Sequential element 706 may receive external data from node 720,and sequential element 710 may drive external data on node 724. PLL 702may substantially align the phase of the clocks on nodes 722 and 704such that data on node 720 is received properly by sequential element706.

[0039] Integrated circuit 700 is shown having a phase lock loopgenerating a clock to operate digital circuits. This can be useful inmany different types of digital integrated circuits. Examples include,but are not limited to, processors such as microprocessors and digitalsignal processors, microcontrollers, sequential memories incorporatingstatic random access memory (SRAM) or dynamic random access memory(DRAM), or the like. Integrated circuit 700 can also be an analogintegrated circuit, such as a communications device that utilizes PLL702 to recover a clock from data.

[0040] The accompanying drawings that form a part hereof show by way ofillustration, and not of limitation, specific embodiments in which thesubject matter may be practiced. The embodiments illustrated aredescribed in sufficient detail to enable those skilled in the art topractice the teachings disclosed herein. Other embodiments may beutilized and derived therefrom, such that structural and logicalsubstitutions and changes may be made without departing from the scopeof this disclosure. This Detailed Description, therefore, is not to betaken in a limiting sense, and the scope of various embodiments isdefined only by the appended claims, along with the full range ofequivalents to which such claims are entitled.

[0041] Such embodiments of the inventive subject matter may be referredto herein, individually and/or collectively, by the term “invention”merely for convenience and without intending to voluntarily limit thescope of this application to any single invention or inventive conceptif more than one is in fact disclosed. Thus, although specificembodiments have been illustrated and described herein, it should beappreciated that any arrangement calculated to achieve the same purposemay be substituted for the specific embodiments shown. This disclosureis intended to cover any and all adaptations or variations of variousembodiments. Combinations of the above embodiments, and otherembodiments not specifically described herein, will be apparent to thoseof skill in the art upon reviewing the above description.

[0042] The Abstract of the Disclosure is provided to comply with 37C.F.R. §1.72(b), requiring an abstract that will allow the reader toquickly ascertain the nature of the technical disclosure. It issubmitted with the understanding that it will not be used to interpretor limit the scope or meaning of the claims. In addition, in theforegoing Detailed Description, it can be seen that various features aregrouped together in a single embodiment for the purpose of streamliningthe disclosure. This method of disclosure is not to be interpreted asreflecting an intention that the claimed embodiments require morefeatures than are expressly recited in each claim. Rather, as thefollowing claims reflect, inventive subject matter lies in less than allfeatures of a single disclosed embodiment. Thus the following claims arehereby incorporated into the Detailed Description, with each claimstanding on its own as a separate embodiment.

What is claimed is:
 1. A circuit, including: a voltage controlledoscillator to generate a differential signal on two nodes; and a phasedetector to compare a phase of the differential signal and a phase of areceived signal, the phase detector including a sampling circuit toperiodically sample voltage values on the two nodes, and a linearvoltage-to-current converter responsive to the voltage values to createa control voltage for the voltage controlled oscillator.
 2. The circuitof claim 1 wherein the linear voltage-to-current converter includes: afirst transconductance amplifier to source current when a positivedifference exists between the voltage values; and a secondtransconductance amplifier to sink current when a negative differenceexists between the voltage values.
 3. The circuit of claim 2, furtherincluding an output stage with series connected transistors having gatescoupled in common.
 4. The circuit of claim 1, wherein the samplingcircuit is configured to sample the voltage values at a transition pointof the received signal.
 5. The circuit of claim 1 further including: afrequency divider coupled to the voltage controlled oscillator and tothe phase detector.
 6. The circuit of claim 5, wherein the frequencydivider is to provide a differential output signal.
 7. An integratedcircuit including a phase lock loop, the phase lock loop comprising: avoltage-to-current circuit to influence a voltage on a capacitor; avoltage controlled oscillator responsive to the voltage on the capacitorto provide a second clock signal; and a sampling circuit responsive to afirst clock signal and the second clock signals, and to generate twovoltage values, a difference of the two voltage values being a functionof a phase difference between the first and second clock signals.
 8. Theintegrated circuit of claim 7, wherein the voltage controlled oscillatorgenerates the second clock signal as a differential signal, and whereinthe sampling circuit samples the differential signal at transitionpoints of the first clock signal to generate the two voltage values. 9.The integrated circuit of claim 7, wherein the first clock signal isreceived as a differential signal, and the sampling circuit samples thedifferential signal at transition points of the second clock signal togenerate the two voltage values.
 10. The integrated circuit of claim 7,wherein the voltage-to-current circuit includes: a firsttransconductance amplifier to source a first current when a positivevoltage differential exists between the two voltage values; a secondtransconductance amplifier to sink a second current when a negativevoltage differential exists between the two voltage values; and anoutput stage coupled between the first transconductance amplifier andthe capacitor, and coupled between the second transconductance amplifierand the capacitor.
 11. The integrated circuit of claim 10, wherein theoutput stage further includes a complementary pair of transistors. 12.An integrated circuit, including: a phase lock loop having avoltage-to-current circuit to influence a voltage on a capacitor; avoltage controlled oscillator responsive to the voltage on the capacitorto provide a second clock signal, and a sampling circuit responsive to afirst clock signal and the second clock signal, and to generate twovoltage values, a difference of the two voltage values being a functionof a phase difference between the first and second clock signals; and aplurality of sequential elements coupled to the phase lock loop.
 13. Theintegrated circuit of claim 12, wherein at least one of the plurality ofsequential elements is to receive data clocked by a signal provided bythe phase lock loop.
 14. The integrated circuit of claim 11, wherein theplurality of sequential elements includes at least one flip-flop. 15.The integrated circuit of claim 11, wherein the voltage-to-currentcircuit includes a first transconductance amplifier coupled to a firstdifferential intput node and a second differential input node, a secondtransconductance amplifier coupled to the first differential intput nodeand the second differential input node, and a first current mirror, asecond current mirror, and a common gate output stage coupled to thefirst transconductance amplifier and the second transconductanceamplifier.
 16. The integrated circuit of claim 15, wherein thevoltage-to-current circuit includes a bias circuit to bias acomplementary pair of transistors included in the common gate outputstage.